Generally, transistors in a bipolar type semiconductor integrated circuit device are produced in an electrically independent island that is separated from adjacent transistors by a pn junction separation method, an oxide film separation method using a selective oxidation technique, or a method utilizing a triple diffusion. Herein, a method of producing an npn transistor by an oxide film separation method will be described. Of course, various separation methods other than this separation method can be used, and transistors may be of pnp types.
FIGS. 10(A) to (E) show the cross-sectional structures of a prior art semiconductor integrated circuit device at major process steps in a prior art production method. The prior art production method will be briefly described in the following paragraphs.
At first, a high impurity density n type (n.sup.+ type) layer 2, which will become a collector embedded layer, is selectively produced on a low impurity density p type (p.sup.- type) silicon substrate 1. Next, an n.sup.- type epitaxial layer 3 will be produced on the silicon substrate 1 and the n.sup.+ type layer 2 (FIG. 10(A)).
Thereafter, an underlying oxide film 101 and a nitride film 201 are produced on a predetermined region of the n.sup.- layer 3, and a channel cutting p type layer 4 is annealed by using the nitride film 201 as a mask. At the same time, a thick separation oxide film 102 is produced by using the nitride film 201 as a mask (FIG. 10(B)).
Next, the nitride film 201, which has been used as a mask at first for the selective oxidation, is removed together with the underlying oxide film 101. Thereafter, an oxide film 103 for ion injection protection is again produced, and a p.sup.+ type layer 5, which will become an external base layer, is produced by using the photoresist film (the photoresist film at this step is not shown) as a mask. Furthermore, the above-described photoresist film is removed, and a photoresist film 301 is again produced in a predetermined configuration, and a p type layer 6 which becomes an active base layer is produced by an ion injection method by using the photoresist film 301 as a mask (FIG. 10(C)).
Subsequently, the photoresist film 301 is removed, and a passivation film 401 generally comprising phosphorous silicate glass coats the surface. A thermal processing is conducted which functions by annealing the base ion injection layers 5 and 6 and sintering the PSG film 401, and an intermediate stage external base layer 51 and an intermediate stage active base layer 61 are produced. Next, an emitter electrode contact hole 70 and a collector electrode contact hole 80 are produced at predetermined regions of the PSG film 401, and an n.sup.+ type layer 7 which will become an emitter layer and an n.sup.+ type layer 8 which will become a collector electrode leading out layer are produced by an ion injection method through the contact holes 70 and 80 (FIG. 10(D)).
Thereafter, the respective ion injection layers are annealed, the external base layer 52 and the active base layer 62 are completed, and the emitter layer 71 and the collector electrode leading out layer 81 are produced. Furthermore, a metal silicide film 501 for preventing the electrode extrusion (such as preventing the reaction between aluminum and silicon) is produced at the respective holes 50, 70 and 80 of the PSG film 401. For this metal silicide film 501, platinum silicide (Pt--Si) or palladium silicide (Pd--Si) are used. Thereafter, a base electrode wiring 9, an emitter electrode wiring 10, and a collector electrode wiring 11 are produced by using a low resistance metal such as aluminum on the metal silicide film 501 (FIG. 10(E)).
The frequency characteristics of a transistor depends on the base-collector capacitance and base resistance, and therefore it is necessary to lower these parameters in order to enhance the frequency characteristics of a transistor. The p.sup.+ type external base layer 52 in the above-described prior art structure is provided so as to lower the base resistance. However, the position of this external base layer 52 is determined by the overlapping in the photolithography process that does not self align with the emitter layer 71, and therefore it has to be produced to some extent apart therefrom which results in the remaining high resistance base layer 62 of a wide region. This result prevents the base resistance from being lowered as much as expected.
Furthermore, the base resistance depends on the distance Dl between the emitter layer 71 and the base electrode leading out aperture 50 as shown in the plain pattern of the transistor produced by the prior art method of FIG. 11. In the prior art device, the distance Dl is the sum of the interval between the base electrode wiring 9 and the emitter electrode wiring 10 and the lengths of the portions of the electrode wirings 9 and 10 extending out from the respective apertures 50 and 70 thereof. Thus, even if the preciseness of the photo etching is enhanced to narrow the electrode wiring interval, the above-described extending out portions inevitably remain, and the base resistance cannot be lowered as much.
Furthermore, although such a double base structure as shown in FIG. 6 is frequently constituted as a method of reducing the base resistance, there are disadvantages that the base region increases due to the leading out of the base electrode, and an increase in the base collector capacitance results.
Furthermore, in the prior art method the plain pattern of the emitter diffusion layer 71 is dependent on the photolithography preciseness. Although the photolithography preciseness of about 1 micron is put into practice by the present highest level photolithography technique, the technique requires a high performance photolithography device and it is quite difficult to produce a further fine pattern. Herein, the reduction of the width of the emitter diffusion layer (emitter width) reduces the emitter area as well the capacitance of an emitter base junction, and further reduces a base resistance (R. M. Warner and J. N. Fordemwolt, "Integrated Circuits," pp. 103-109, McGraw-Hill, New York, 1985). Accordingly, although fine patterning of the emitter width is required in order to improve the frequency characteristics, there was a problem that the fine patterning of the emitter width is restricted by the photolithography preciseness in the prior art method.
FIG. 13(A) to FIG. 13(I) show cross-sectional views at the major production process steps of a second prior art method of producing a semiconductor integrated circuit device. This second prior art production method will be described in the following paragraphs.
FIG. 13(A)
At first, a high impurity density n type (n.sup.+ type) layer 2, which becomes a collector embedded layer, is selectively produced on a low impurity density p type (p.sup.- type) silicon substrate 1. Thereafter, a low impurity density n type (n.sup.- type) epitaxial layer 3 is grown thereon.
FIG. 13(B)
An underlying oxide film 1101 is produced on the epitaxial layer 3, and a nitride film 1201 having a predetermined configuration is produced on the underlying oxide film 1101. A thick separation oxide film 1102 is produced by conducting a selective oxidation by using the nitride film 1201 as a mask. At the same time, a channel cutting p type layer 4 is produced below the separation oxide film 1102.
FIG. 13(C)
After removing the nitride film 1201 which has been used as a selective oxidation mask together with the underlying oxide film 1101, an oxide film 1103 for ion injection protection is produced again. A p type layer 6 which will become an active base layer is produced by conducting an ion injection by using a photoresist film produced on the oxide film 1103 as a mask (the photoresist film at this step is not shown). Thereafter, an oxide film 1103 at the neighborhood of the region which will become a base electrode aperture is removed. Next, a silicon film 1601 is coated over the exposed entire surface. Herein, a monocrystalline silicon film, a polycrystalline silicon film, or an amorphous silicon film is used as the silicon film.
FIG. 13(D)
An intermediate stage active base region 61 is produced at the p type layer 6 by conducting a sintering process after introducing p type impurities into the entire surface of the silicon film 1601. At the same time, an external base region 51 is produced by conducting an impurity diffusion from the p type impurities included in the silicon film 1601. Thereafter, the silicon film 1601 is selectively etched and removed, and a silicon film remains on the external base region 51 and the separation oxide film 1102. An oxide film 1105 is produced on a position where the oxide film 1103 has been produced, and an oxide film 1106 is produced over the remaining silicon film 1601 by again conducting an oxidation process, and a phosphorous silicate glass film 1401 is produced on the entire surface.
FIG. 13(E)
In conducting a selective etching by using a photoresist film (not shown), mask apertures are produced by removing the oxide film 1105 and the PSG film 1401 on the regions which are to be an emitter layer and a collector electrode leading out layer. Next, a silicon film 1602 is coated over the entire surface, n type impurities are ion injected into the silicon film 1602 at a high concentration. Next, driving of injected impurities is conducted to diffuse impurities into the substrate surface from the silicon film 1602. Thereby, an n+type layer 71 is produced which will become an emitter layer and an n.sup.+ type layer 81 is produced which will become a collector electrode leading out layer. Then, impurities are also driven to the external base region 51 to produce an external base region 52.
FIG. 13(F)
A selective etching of the silicon film 1602 is conducted so that the silicon film portions 1602a and 1603, which will become impurity diffusion sources, remain. Next, aperturing of a contact hole for a base contact is conducted by using the resist film 1302, which is patterned in a predetermined configuration, as a mask. Then, the resist film 1302 is produced to expose a portion of the silicon film 1602a for producing the emitter layer, the base contact and the oxide film 1106 and the PSG film 1401 on the silicon film 1601 following the base contact which is etched and removed by using the exposed silicon film 1602a as a mask.
FIG. 13(G)
An oxidation at a low temperature (about 800.degree. C. to 900.degree. C.) is conducted to produce a thick oxide film 1108 on the polysilicon films 1602a and 1603 and the n.sup.+ layers 71 and 81, and a thin oxide film 1107 on the p type region 62 and the p.sup.+ type silicon film 1601. This is produced with the use of the well known fact that the lower the temperature is, the more the acceleration oxidation is conducted in the silicon substrate and in the silicon film including phosphor and arsenic at n type impurities at a high concentration.
FIG. 13(H)
Only the thin oxide film 1107 is washed out. Next, a metal layer (not shown) is produced by the use of a vapor plating method or a sputtering method on the entire surface with the use of metals such as Pt, Pd, Ti, W, and Mo which produce a metal silicide with silicon or polysilicon film. Thereafter, a sintering process is conducted to produce metal silicide films 1501 and 1502 on the exposed surface of the silicon substrate and the silicon film 1601. Thereafter, the metal layer is removed by etching, such as aqua regia, so that the metal silicide film remains.
FIG. 13(I)
After a passivation nitride film 1202 (an oxide film may be used) is coated over, selective etching is executed to the nitride film 1202 and the thick oxide film 1108. The base electrode contract hole 50, the emitter electrode contact hole 70, and the collector electrode contact hole 80 are apertured. Next, a base electrode wiring 9, an emitter electrode wiring 10, and a collector electrode wiring 11 are respectively produced by using low resistance metal such as aluminum.
FIG. 14 shows a plain pattern of a transistor produced through the production process shown in FIG. 13(A) to FIG. 13(I). In FIG. 14, the distance C designates a distance between the emitter layer 71 and the polysilicon film 1601 connected to the base electrode 9, and the distance D designates a distance between the emitter layer 71 and the separation oxide film 1102. The photolithography for the aperturing, which produces the emitter layer 71 (production of the aperture portion), is conducted in alignment with either of the patterns of the separation oxide film 1102 or the polysilicon film 1601, and the interval between either of them and the emitter layer 71 must be made larger than the overlapping margin of the photolithography (an overlapping margin corresponding to twice the photolithography is required). Because the photolithography for the aperturing which produces the emitter layer 71 is generally conducted in alignment with the pattern of the separation oxide film 1102, it is necessary to increase the distance C (to a larger value than about twice of the overlapping margin). This increase in the distance C causes an increase in the base area and results in increases of a base collector capacitance.
FIG. 15 shows cross-sections illustrating variations in the distance between the emitter layer and the polysilicon film, which is connected to the base electrode, caused by the overlapping preciseness of the photolithography. The dependency of the distance C on the photolithography overlapping preciseness will be described in the following paragraphs.
As shown in FIG. 15(A), usually the polysilicon film 1601, which will become a base electrode, is aligned by photolithography with the separation edge (the end portion of the separation oxide film 1102) as shown in the drawing by an arrow A. The emitter contact is also aligned by photolithography with the separation edge (arrow B), and the silicon film 1602a, which will become an emitter electrode, is aligned by photolithography with the contact pattern. Accordingly, the distance between the silicon films (corresponding to the distance C of FIG. 14) is determined by the overlapping preciseness of the photolithography. In the worst case, the inter-silicon film distance C greatly varies in a range from below half to three times of the distance in the normal case as shown in FIGS. 15(B) and (C).
FIG. 16 shows a plain pattern of a transistor which adopts a double base structure having the above-described distances C at both sides of the emitter so that the variation of the above-described distance C is suppressed.
In this double base structure, an active base region 62 surrounds the emitter layer 71. The silicon films 1601 on the external base region are produced between the emitter layer and are connected to the base electrode wiring 11 through both side contact holes 50.
FIG. 17 shows a cross-sectional structure of a transistor element having a double base structure which is obtained by the photolithography in the production of the emitter layer in a case where the worst photolithography is conducted. Even when the photolithography overlapping in the production of the emitter layer becomes worse as shown in FIG. 17, by adopting a double base structure as shown in FIG. 16, the distance E between the silicon film 1601, which is connected to the base electrode, and the emitter diffusion layer 71 is required to be set at the same value as designed. When such a double base structure is adopted, the inter-silicon film interval C (the distance between the emitter layer and the silicon film which is connected to the base electrode) becomes one including the photolithography overlapping margin, and the incremental portion of the extra base area approximately doubles by adopting such a double base structure. This becomes a heavy obstruction to the enhancement of the frequency characteristics in the transistor element.